1. Field of the Invention
The present invention relates to a method for modeling a semiconductor structure. In particular, the present invention relates to a method for modeling capacitance in conductive regions in a semiconductor substrate.
2. Discussion of the Related Art
Accurate extraction of impedance (e.g., capacitance) is essential for evaluating and predicting the performance of an integrated circuit manufactured under a given manufacturing process. Accurate values of impedance can be obtained only with accurate modeling of semiconductor structures manufactured under that process. A number of techniques for accurate extraction of impedance from interconnect structures of a semiconductor structure are disclosed in U.S. Pat. No. 5,901,063 (the "'063 Patent"), entitled "System and Method for Extracting Parasitic Impedance From an Integrated Circuit Layout," Ser. No. 08/804,524, filed on Feb. 21, 1997, issued on May 4, 1999, and assigned to Frequency Technology, Inc., which is also the Assignee of the present application. The disclosure of the '063 Patent is hereby incorporated by reference in its entirety.
FIGS. 1a and 1b depict corresponding cross-sectional and top views of a typical CMOS semiconductor structure 100 using a conventional thermal oxide isolation technique, showing only two conductor layers 101 and 102 above the substrate. In more recent integrated circuit processes, the number of conductor layers is typically more numerous than is shown in FIGS. 1a and 1b, often consisting of multiple layers of polysilicon and metal. FIGS. 1a and 1b show two conductor layers merely for illustrative purposes. As shown in FIGS. 1a and 1b, a semiconductor substrate 106 includes doped regions 106a and 106b of opposite conductivities, forming a P-well and an N-well for forming N-channel and P-channel transistors respectively. Thermal oxide regions 103a, 103b, 103c and 103d are provided to electrically isolate semiconductor regions 108a, 108b and 108c from each other. Thermal oxide regions 103a-103d are typically formed by the well-known LOCOS process that oxidize the substrate silicon surface at high temperature. Devices, such as transistors and capacitors, are formed within the semiconductor regions.
The first conductor layer 101 above substrate 106 is used to provide both device electrodes and interconnect conductor traces between device electrodes. For example, in FIGS. 1a and 1b, conductors 101b, 101c and 101e may be used as gate electrodes, and conductors 101a and 101d can be used as interconnect conductor traces. Conductor layer 101 is typically provided by doped polysilicon. Conductor layer 101 is isolated from substrate 106 by one or more dielectric layers 111. Conductors 101a and 101d are routed over thermal oxide regions 103a and 103c. To form diffusion (e.g., source and drain regions for an active device) regions, a well-known self-aligned process step introduces impurities ("dopants") into the regions 104a, 104b, 104c, 104d, 104e and 104f, using interconnect conductor layer 101 as a masking layer.
A layer of dielectric 109 is provided to isolate conductor layer 101 from conductor layer 102. Conductor layer 102 can be provided by either polysilicon or metal. Openings in dielectric layers 109 and 111 are provided and filled with a conductive material 105 to electrically connect (as "contacts") conductors in conductor layer 101 or diffusion regions 104 with conductors in conductor layer 102. For example, contacts 105a and 105b are provided to connect conductors 102a and 102b to diffusion regions 104a and 104b, and contacts 105c and 105d are provided to electrically connect conductors 102c and 102e to conductors 101c and 101e, respectively.
Because thermal oxide (e.g., thermal oxide formed under the LOCOS process) is much thicker than the portion of silicon substrate from which the thermal oxide is formed, thermal oxidation results in an undulating surface topography at the surface of the substrate, as shown in Figure la. Subsequent growth or depositions of materials, such as dielectric layers 111, conductor 101 and dielectric layer 109, are typically conformal to this surface topography, as can be seen in FIG. 1a. In the prior art, the capacitance in an active area between an electrode and a conductive portion of the substrate (e.g., a source or a drain region) is evaluated with the operation of the active device, and a capacitance between a conductor line in the "field region" (e.g., thermal oxide regions 103a and 103c) and a conductive portion of the substrate is simply ignored because of the width of the field region. Under thermal oxide isolation, the width of the field region is relatively large because of the so-called bird's beak structure (e.g., bird's beak 112).
Recently, the width of the field region is greatly reduced by using deposited oxide isolation. One deposited oxide isolation technique is known as "shallow trench isolation" (STI), which is illustrated by FIGS. 2a and 2b. FIGS. 2a and 2b depict corresponding cross-sectional and top views of a semiconductor structure 200, which includes two interconnect conductor layers 201 and 202. (To simplify discussion of the figures, like reference numerals are provided like features). Unlike semiconductor structure 100, however, rather than providing thermal oxide regions 103a-103d, shallow trenches are etched in substrate 106 to isolate areas 108a, 108b and 108c. An oxide is then deposited over the surface of substrate 106 and to fill the trenches. A chemical-mechanical polishing (CMP) step planarizes the surface of substrate 106 by polishing the deposited oxide away from the surface of substrate 106, thus providing the filled STI trenches 203a, 203b, 203c and 203d. Dielectric layers 111, 109 and 110, conductor layers 201 and 202, and contacts layer 105 can be provided in substantially the same manner as dielectric layers 111, 109 and 110, conductor layers 101 and 102 and contacts layer 105, respectively, as discussed above with respect to FIGS. 1a and 1b. Alternatively, after each layer of conductor material (i.e., conductor layers 201 and 202) is deposited, a CMP step can be applied to planarize the resulting surface, as shown in FIG. 2a.
Because STI trenches 203a-203d can be made much narrower than corresponding thermal oxide regions 103a-103d, capacitance between a conductor in the first conductor layer 201 (e.g., conductor 201a or 201d) and a conducting portion of the substrate(e.g., any of diffusion regions 104a, 104c-104f) can no longer be ignored. In addition, even though one goal of CMP is to provide a completely planarized surface, because of selectivity of the process and local non-uniformity, "dishing" can often occur. At submicron feature sizes, to achieve high performance, accurate extraction of impedance can be achieved only with accurate modeling of the conductor layers and the substrate.